Rajagopal Anantharaman, Karibasappa Kwadiki, Vasundara Patel Kerehalli Shankar Rao
Hardware Implementation Analysis of Min-Sum Decoders
Číslo: 2/2019
Periodikum: Advances in Electrical and Electronic Engineering
DOI: 10.15598/aeee.v17i2.3042
Klíčová slova: Bit Error Rate (BER); Field Programmable Gate Array (FPGA); Logarithmic Sum Product (LogSP); Low Density Parity Check (LDPC); Signal to Noise Ratio (SNR); Sum Product Algorithm (SPA).
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