An Embedded Implementation of Discrete Zolotarev Transform Using Hardware-Software Codesign

J. Kubak, J. Stastny, P. Sovka

An Embedded Implementation of Discrete Zolotarev Transform Using Hardware-Software Codesign

Číslo: 2/2021
Periodikum: Radioengineering Journal
DOI: 10.13164/re.2021.0364

Klíčová slova: Discrete Zolotarev Transform (DZT), Approximated Discrete Zolotarev Transform (ADZT), embedded hardware, hardware-software co-design, Field Programmable Gate Array (FPGA), VHDL

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Anotace: The Discrete Zolotarev Transform (DZT) brings an improvement in the field of spectral analysis of non-stationary signals. However, the transformation algorithm called Approximated Discrete Zolotarev Transform (ADZT) suffers from high computational complexity. The Short Time ADZT (STADZT) requires high segment length, 512 samples, and more, while high segment overlap to prevent information loss, 75 % at least. The STADZT requirements along with the ADZT algorithm computational complexity result in a rather high computational load. The algorithm computational complexity, behavior, and quantization error impacts are analyzed. We present a solution which deals with high computational load employing co-design methods targeting Field Programmable Gate Array (FPGA). The system is able to compute one-shot DZT spectrum 2 048 samples long in ≈ 22ms. Real-time STADZT spectrum of a mono audio signal of 16 kHz sampling frequency can be computed with overlap of 91 %.